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1 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners. 1.2a high efficiency buck-boost regulator ISL9110A the ISL9110A is a highly-integrated buck-boost switching regulator that accepts input volt ages either above or below the regulated output voltage. unlike other buck-boost regulators, this regulator automatically transi tions between operating modes without significant output disturbance. this part is capable of delivering up to 1.2a output current, and provides excellent efficiency due to its fully synchronous 4-switch architecture. no-load quiescent current of only 35a also optimizes efficiency under ligh t-load conditions. forced pwm and/or synchronization to an external clock may also be selected for noise sensitive applications. the ISL9110A is designed for standalone applications and supports 3.3v and 5v fixed output voltages or variable output voltages with an external resistor divider. output voltages as low as 1v, or as high as 5.2v are supported using an external resistor divider. the ISL9110A requires only a single inductor and very few external components. power supply solution size is minimized by a 2.4mm x 1.6mm wlcsp package and a 2.5mhz switching frequency, which further redu ces the size of external components. features ? accepts input voltages above or below regulated output voltage ? automatic and seamless transitions between buck and boost modes ? input voltage range: 1.8v to 5.5v ? output current: up to 1.2a ? high efficiency: up to 95% ? 35a quiescent current maxi mizes light-load efficiency ? 2.5mhz switching frequency mi nimizes external component size ? selectable forced-pwm mode and external synchronization ? fully protected for overcurrent, over-temperature and undervoltage ? small 2.4mmx1.6mm wlcsp package applications ? regulated 3.3v from a single li-ion battery ? smart phones and tablet computers ? handheld devices ?point-of-load regulators related literature ? see an1750 ?ISL9110A evaluation board user guide? figure 1. typical application figure 2. efficiency v out = 3.3v/1a vout a5 fb d5 c2 10f bat pg status outputs d2 d1 pvin v in = 1.8v to 5.5v vin b1 c1 mode en d3 c2 c1 10f ISL9110Aiitnz d4 c3 lx1 lx2 b 2 a 4 l1 2.2h b5 gnd c5 b3 a3 c4 pgnd b 4 a 2 a1 i out (a) efficiency (%) 70 75 80 85 90 95 100 0.01 0.05 0.25 1.25 v in = 5v v in = 2.5v v in = 3v v out = 3.3v june 8, 2012 fn8299.1
ISL9110A 2 fn8299.1 june 8, 2012 block diagram pin configurations ISL9110A (20 ball wlcsp) top view osc error amp pvin pwm control pvin monitor lx1 v ref ref reverse current vout a1 b2 b4 lx2 gate drivers & anti- shoot thru c1 vin thermal shutdown current detect b5 vout monitor c2 en d5 fb a3 pgnd c5 gnd en en en en en vout clamp d2 bat d3 mode/sync d1 pg voltage prog. en soft discharge a5 a4 a2 b1 b3 c3 c4 d4 a1 b1 a2 b2 c1 d1 c2 d2 a3 b3 a4 b4 c3 d3 c4 d4 a5 b5 c5 d5 pin descriptions pin # pin names description a5, b5 vout buck/boost output. connect a 10f capacitor to pgnd. a4, b4 lx2 inductor connection, output side. a3, b3, c3, c4 pgnd power ground for high switching current. a2, b2 lx1 inductor connection, input side. a1, b1 pvin power input. range: 1.8v to 5.5v. connect a 10f capacitor to pgnd. c1 vin supply input. range: 1.8v to 5.5v. d1 pg open drain output. provides output-power-good status. d2 bat open drain output. provides input-power-good status. c2 en logic input, drive high to enable device. d3 mode/ sync logic input, high for auto pfm mode. low for forced pwm operation. ext. clock sync input. range: 2.75mhz to 3.25mhz. c5, d4 gnd analog ground pin. d5 fb voltage feedback pin.
ISL9110A 3 fn8299.1 june 8, 2012 ordering information part number (note 3) part marking v out (v) temp range (c) package tape and reel (pb-free) pkg. dwg. # ISL9110Aiitnz-t (notes 1, 2) dzbe 3.3 -40 to +85 20 ball wlcsp w4x5.20a ISL9110Aiitaz-t (notes 1, 2) dzbd adj -40 to +85 20 ball wlcsp w4x5.20a ISL9110Aiitnz-eval1z evaluation board ISL9110Aiitaz-eval1z evaluation board notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free wlcsp and bga packaged products employ special pb-free material sets; molding compounds/die attach mat erials and snagcu - e1 solder ball terminals, which are rohs compliant an d compatible with both snpb and pb-free soldering operations. int ersil pb-free wlcsp and bga packaged products are msl classified at pb-free pe ak reflow temperatures that meet or exceed the pb-free requirem ents of ipc/jedec j std-020. 3. for moisture sensitivity level (msl), please see device information page for ISL9110A . for more information on msl please see techbrief tb363 .
ISL9110A 4 fn8299.1 june 8, 2012 table of contents applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 related literature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 absolute maximum ratings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 recommended operating conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 analog specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 typical performance curves. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 internal supply and references. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 enable input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 soft discharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 por sequence and soft-start. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 short circuit protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 pg status output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 bat status output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 ultrasonic mode (available upon request) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 external synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 buck-boost conversion topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 pwm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 pfm operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 operation with vin close to vout. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 output voltage programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 applications information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 component selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 output voltage programming, adj. version . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 feed-forward capacitor selection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 non-adjustable version fb pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 pvin and vout capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 application example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 application example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 recommended pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 package outline drawing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
ISL9110A 5 fn8299.1 june 8, 2012 absolute maximum rating s thermal information pvin, vin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v lx1, lx2 (note 6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v fb (adjustable version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 2.7v fb (fixed v out versions) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v gnd, pgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 0.3v all other pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to 6.5v esd rating human body model (tested per jesd22-a114e) . . . . . . . . . . . . . . . . 3kv machine model (tested per jesd22-a115-a) . . . . . . . . . . . . . . . . . 250v latch up (tested per jesd-78b; class 2, level a) . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 20 ball wlscp package (notes 4, 5) . . . . 66 1 maximum junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+125c storage temperature range. . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp recommended operating conditions ambient temperature range . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c supply voltage range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.8v to 5.5v load current range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0a to 1.2a caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 4. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379 5. for jc , the ?case temp? location is taken at the package top center. 6. lx1 and lx2 pins can withstand switching tran sients of -1.5v for 100ns, and 7v for 20ms. analog specifications v vin = v pvin = v en = 3.6v, v out = 3.3v, l1 = 2.2h, c1 = c2 = 10f, t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. symbol parameter test conditions min (note 7) typ (note 8) max (note 7) units power supply v in input voltage range 1.8 5.5 v v uvlo v in undervoltage lockout threshold rising 1.725 1.775 v falling 1.550 1.650 v i vin v in supply current pfm mode, no external load on vout (note 9) 35 60 a i sd v in supply current, shutdown en = gnd, v in = 3.6v 0.05 1.0 a output voltage regulation v out output voltage range ISL9110Aiitaz, i out = 100ma 1.00 5.20 v output voltage accuracy v in = 3.7v, v out = 3.3v, i out = 0ma, pwm mode -2 +2 % v in = 3.7v, v out = 3.3v, i out = 1ma, pfm mode -3 +4 % v fb fb pin voltage regulation for adjustable output version 0.79 0.80 0.81 v i fb fb pin bias current for adjustable output version 1 a v out / v in line regulation, pwm mode i out = 500ma, v out = 3.3v, mode = gnd, v in step from 2.3v to 5.5v 0.005 mv/mv v out / i out load regulation, pwm mode v in = 3.7v, v out = 3.3v, mode = gnd, i out step from 0ma to 500ma 0.005 mv/ma v out / v i line regulation, pfm mode i out = 100ma, v out = 3.3v, mode = v in , v in step from 2.3v to 5.5v 12.5 mv/v v out / i out load regulation, pfm mode v in = 3.7v, v out = 3.3v, mode = v in , i out step from 0ma to 100ma 0.4 mv/ma v clamp output voltage clamp rising, v in = 3.6v 5.25 5.95 v output voltage clamp hysteresis v in = 3.6v 400 mv dc/dc switching specifications f sw oscillator frequency 2.25 2.50 2.75 mhz t onmin minimum on time 80 ns i pfetleak lx1 pin leakage current -1 1 a i nfetleak lx2 pin leakage current -1 1 a
ISL9110A 6 fn8299.1 june 8, 2012 soft-start and soft discharge t ss soft-start time time from when en signal asserts to when output voltage ramp starts. 1ms time from when output voltage ramp starts to when output voltage reaches 95% of its nominal value with device operating in buck mode. v in = 4v, v out = 3.3v, i o = 200ma 1ms time from when output voltage ramp starts to when output voltage reaches 95% of its nominal value with device operating in boost mode. v in = 2v, v out = 3.3v, i o = 200ma 2ms r dischg v out soft-discharge on-resistance v in = 3.6v, en < vil 120 power mosfet r dson_p p-channel mosfet on-resistance v in = 3.6v, i o = 200ma 0.10 0.17 v in = 2.5v, i o = 200ma 0.13 0.23 r dson_n n-channel mosfet on-resistance v in = 3.6v, i o = 200ma 0.09 0.15 v in = 2.5v, i o = 200ma 0.11 0.23 i pk_lmt p-channel mosfet peak current limit v in = 3.6v 2.0 2.4 2.8 a pfm/pwm transition load current threshold, pfm to pwm v in = 3.6v, v out = 3.3v 200 ma load current threshold, pwm to pfm v in = 3.6v, v out = 3.3v 75 ma external synchronization frequency range 2.75 3.25 mhz thermal shutdown 155 c thermal shutdown hysteresis 30 c battery monitor and power good comparators vt bmon battery monitor voltage threshold 1.85 2.0 2.15 v vh bmon battery monitor voltage hysteresis 100 mv t bmon battery monitor debounce time 25 s pg delay time (rising) 1ms pg delay time (falling) 20 s minimum supply voltage for valid pg signal en = vin 1.2 v pg rnglr pg range - lower (rising) percentage of programmed voltage 90 % pg rnglf pg range - lower (falling) percentage of programmed voltage 87 % pg rngur pg range - upper (rising) percentage of programmed voltage 112 % pg rnguf pg range - upper (falling) percentage of programmed voltage 110 % compliance voltage - pg, bat v in = 3.6v, i sink = 1ma 0.3 v logic inputs i leak input leakage 0.05 1 a v ih input high voltage 1.4 v v il input low voltage 0.4 v notes: 7. parameters with min and/or max limits are 100% tested at +25c , unless otherwise specified. te mperature limits established by characterization and are not production tested. 8. typical values are for t a = +25c and v in = 3.6v. 9. quiescent current measurements are taken when the output is not switching. analog specifications v vin = v pvin = v en = 3.6v, v out = 3.3v, l1 = 2.2h, c1 = c2 = 10f, t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) symbol parameter test conditions min (note 7) typ (note 8) max (note 7) units
ISL9110A 7 fn8299.1 june 8, 2012 typical performance curves figure 3. efficiency vs output current, v out = 2v figure 4. efficiency vs output current, v out = 3.3v figure 5. efficiency vs output current, v out = 4v figure 6. maximum output current vs input voltage figure 7. pwm mode quiescent current, v out = 3.3v, no load figure 8. pfm mode quiescent current, v out = 3.3v, no load 70 75 80 85 90 95 100 0.01 0.05 0.25 1.25 i out (a) efficiency (%) v in = 5v v in = 4.5v v in = 2.5v v in = 3v v in = 2v v out = 2.0v v in = 4v i out (a) efficiency (%) 70 75 80 85 90 95 100 0.01 0.05 0.25 1.25 v in = 5v v in = 4.5v v in = 4v v in = 2.5v v in = 2v v out = 3.3v v in = 3v 70 75 80 85 90 95 100 0.01 0.05 0.25 1.25 i out (a) efficiency (%) v in = 5v v in = 4.5v v in = 2.5v v in = 3v v in = 2v v out = 4.0v v in = 4v 0.0 0.5 1.0 1.5 2.0 2.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 i out (a) v in (v) v out = 5v v out = 3.3v v out = 2v 4 5 6 7 8 9 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 quiescent current (ma) v in (v) -40c 0c +25c +85c v out = 3.3v 30 35 40 45 50 55 60 1.5 2.5 3.5 4.5 5.5 -40c 0c +25c +85c v out = 3.3v quiescent current (a) v in (v)
ISL9110A 8 fn8299.1 june 8, 2012 figure 9. steady state transition from buck to boos t figure 10. steady state transition from boost to buck figure 11. steady state v in near v out figure 12. input transient figure 13. transient load response figure 14. transient load response typical performance curves (continued) lx1 5v/div 5v/div lx2 50mv/div vout 0.5a/div current inductor 400s/div v in = 4.5v 2.5v v out = 3.3v i out = 500ma lx1 5v/div 5v/div lx2 50mv/div vout 0.5a/div current inductor 400s/div v in = 2.5v 4.5v v out = 3.3v i out = 500ma lx1 2v/div 2v/div lx2 50mv/div vout 0.5a/div current inductor 400ns/div v in = 3.6v v out = 3.3v i out = 0.6a 50mv/div vout 2v/div vin 50s/div v in = 4.5v 2.5v 4.5v v out = 3.3v i out = 400ma 0.1v/div vout 0.5a/div current inductor 100s/div lx1 5v/div 5v/div lx2 v in = 2v v out = 3.3v i out = 0a to 0.4a lx1 5v/div 5v/div lx2 0.1v/div vout 0.5a/div current inductor 100s/div v in = 3.6v v out = 3.3v i out = 0a to 1a
ISL9110A 9 fn8299.1 june 8, 2012 figure 15. switching waveforms, boost mode figure 16. switching waveforms, buck mode figure 17. nfet r ds(on) vs input voltage figure 18. pfet r ds(on) vs input voltage figure 19. v ref vs temperature, t a = -40c to +85c figure 20. output voltage vs v in voltage (v out = 3.3v) typical performance curves (continued) lx1 2v/div 2v/div lx2 10mv/div vout 0.5a/div current inductor 400ns/div v in = 2.5v v out = 3.3v i out = 500ma lx1 5v/div 5v/div lx2 10mv/div vout 0.5a/div current inductor 400ns/div v in = 4.5v v out = 3.3v i out = 1a 0.00 0.05 0.10 0.15 0.20 0.25 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40c 0c +40c +85c r ds(on) ( ? ) v in (v) 0.00 0.05 0.10 0.15 0.20 0.25 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 -40c 0c +40c +85c r ds(on) ( ? ) v in (v) 0.790 0.795 0.800 0.805 0.810 -40-20 0 20406080100 v ref (v) temperature (c) 3.270 3.275 3.280 3.285 3.290 1.5 2.5 3.5 4.5 5.5 i out = 0.1a (pfm) no load (pfm) i out = 1.2a (pwm) i out = 0.8a (pwm) i out = 0.4a (pwm) v out (v) v in (v)
ISL9110A 10 fn8299.1 june 8, 2012 figure 21. soft-start, v in = 4v, v out = 3.3v figure 22. soft-start, v in = 2v, v out = 3.3v figure 23. output voltage vs load current (v in = 2.5v, v out = 3.3v, auto pfm/pwm mode) figure 24. output voltage vs load current (v in = 4.5v, v out = 3.3v, auto pfm/pwm mode) figure 25. output soft-discharge figure 26. pf m to pwm mode change threshold current vs input voltage (v out = 3.3v) typical performance curves (continued) lx1 2v/div 2v/div lx2 2v/div vout 2v/div en 400s/div v in = 4v v out = 3.3v i out = 200ma lx1 2v/div 2v/div lx2 2v/div vout 2v/div en 400s/div v in = 2v v out = 3.3v i out = 200ma 3.280 3.285 3.290 3.295 3.300 3.305 3.310 3.315 0.00.10.20.30.40.5 v out (v) i out (ma) load current rising load current falling 3.280 3.285 3.290 3.295 3.300 3.305 3.310 0.0 0.1 0.2 0.3 0.4 0.5 v out (v) i out (ma) load current rising load current falling 1v/div vout 1v/div en 4ms/div v in = 3.7v v out = 3.3v 0.00 0.05 0.10 0.15 0.20 0.25 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 i out (a) v in (v) pfm to pwm transition pwm to pfm transition
ISL9110A 11 fn8299.1 june 8, 2012 functional description functional overview refer to the ?block diagram? on page 2. the ISL9110A implements a complete buck boost switching regulator, with pwm controller, internal switches, references, protection circuitry, and control inputs. the pwm controller automatically switches between buck and boost modes as necessary to maintain a steady output voltage, with changing input voltages and dynamic external loads. the ISL9110A provides output-power-good and input-power-good open-drain status outputs on pins 7 and 8. internal supply and references referring to the ?block diagram? on page 2, the ISL9110A provides two power input pins. the pvin pin supplies input power to the dc/dc converter, while the vin pin provides operating voltage source required for stable v ref generation. separate ground pins (gnd and pgnd) are provided to avoid problems caused by ground shift due to the high switching currents. enable input a master enable pin en allows the device to be enabled. driving en low invokes a power-down mode, where most internal device functions, including input and ou tput power good detection, are disabled. soft discharge when the device is disabled by driving en low, an internal resistor between v out and gnd is activated. this internal resistor has a typical 120 ? resistance. por sequence and soft-start bringing the en pin high allows the device to power-up. a number of events occur during the start-up sequence. the internal voltage reference powers up, and stabilizes. the device then starts operating. there is a typical 1ms delay between assertion of the en pin and the start of switching regulator soft-start ramp. the soft-start feature minimizes output voltage overshoot and input inrush currents. during soft -start, the reference voltage is ramped to provide a ramping v out voltage. while output voltage is lower than approximately 20% of the target output voltage, switching frequency is reduced to a fraction of the normal switching frequency to aid in producing low duty cycles necessary to avoid input inrush current sp ikes. once the output voltage exceeds 20% of the target voltage, switching frequency is increased to its nominal value. when the target output voltage is higher than the input voltage, there will be a transition from buck mode to boost mode during the soft-start sequence. at the ti me of this transition, the ramp rate of the reference voltage is decreased, such that the output voltage slew rate is decreased. this provides a slower output voltage slew rate. the v out ramp time is not constant for all operating conditions. soft-start into boost mode will take longer than soft-start into buck mode. the total soft-start time into buck operating mode is typically 2ms, whereas the typical soft-start time into boost mode operating mode is typically 3ms. increasing the load current will increase these typical soft-start times. overcurrent protection when the current in the p-channel mosfet is sensed to reach the current limit for 16 consecutive switching cycles, the internal protection circuit is triggered, and switching is stopped for approximately 20ms. the device then performs a soft-start cycle. if the external output overcurrent condition exists after the soft-start cycle, the device will again detect 16 consecutive switching cycles reaching the peak current threshold. the process will repeat as long as the external overcurrent condition is present. this behavior is called ?hiccup mode?. short circuit protection the ISL9110A provides short-circui t protection by monitoring the feedback voltage. when feedback voltage is sensed to be lower than a certain threshold, the pwm oscillator frequency is reduced in order to protect the device from damage. the p-channel mosfet peak current lim it remains active during this state. undervoltage lockout the undervoltage lockout (uvlo) feature prevents abnormal operation in the event that the supply voltage is too low to guarantee proper operation. when the v in voltage falls below the uvlo threshold, the re gulator is disabled. pg status output an open drain output-power-good signal is provided in the ISL9110A. an internal window comparator is used to detect when v out is significantly higher or lower than the target output voltage. the pg output will be driven low when sensed v out voltage is outside of this ?power good? window. when v out voltage is inside the ?power-good? window, the pg pin goes hi-z. the pg detection circuit detects this condition by monitoring voltage on the fb pin. hysteresis is provided for the upper and lower pg thresholds to avoid oscillation of the pg output. bat status output the ISL9110A provides an open drain input-power-good status output. the bat status pin will be driven low when v in rises above the vt bmon threshold. the bat status output goes hi-z when v bat falls below the vt bmon threshold. hysteresis is provided for the vt bmon threshold to avoid oscillation of the bat output. ultrasonic mode (available upon request) the ISL9110A provides an ultrason ic mode that can be enabled during ic manufacturing upon request. in ultrasonic mode, the pfm switch ing frequency is forced to be above the audio frequency range. this ultrasonic mode applies only to pfm mode operation. when enabled, the pfm mode switching frequency is forced well above the audio frequency range (f sw becomes typically 60khz). this mode of operation, however, reduces the efficiency at light load.
ISL9110A 12 fn8299.1 june 8, 2012 thermal shutdown a built-in thermal protection feature protects the ISL9110A, if the die temperature reaches +155c (typical). at this die temperature, the regulator is completely shut down. the die temperature continues to be moni tored in this thermal-shutdown mode. when the die temperature falls to +125c (typical), the device will resume normal operation. when exiting thermal shutdown, the ISL9110A will execute its soft-start sequence. external synchronization an external sync feature is provid ed. applying a clock signal with a frequency between 2.75mhz an d 3.25mhz at the mode/sync input forces the ISL9110A to synchronize to this external clock. the mode/sync input supports standard logic levels. buck-boost conversion topology the ISL9110A operates in either buck or boost mode. when operating in conditions where v in is close to v out , the ISL9110A alternates between buck and boost mode as necessary to provide a regulated output voltage. figure 27 shows a simplified di agram of the internal switches and external inductor. pwm operation in buck pwm mode, switch d is continuously closed, and switch c is continuously open. switches a and b operate as a synchronous buck converter when in this mode. in boost pwm mode, switch a remains closed and switch b remains open. switches c and d operate as a synchronous boost converter when in this mode. pfm operation during pfm operation in buck mode, switch d is continuously closed, and switch c is continuously open. switches a and b operate in discontinuous mo de during pfm operation. during pfm operation in boost mode, the ISL9110A closes switch a and switch c to ramp up the current in the inductor. when inductor current reaches a certain threshold, the device turns off switches a and c, then turns on switches b and d. with switches b and d closed, output voltage increases as the inductor current ramps down. in most operating conditions, ther e will be multiple pfm pulses to charge up the output capacito r. these pulses continue until v out has achieved the upper threshold of the pfm hysteretic controller. switching then stops, and remains stopped until v out decays to the lower threshold of the hysteretic pfm controller. operation with v in close to v out when the output voltage is close to the input voltage, the ISL9110A will rapidly and smoothly switch from boost to buck mode as needed to maintain the regulated output voltage. this behavior provides excellent efficiency and very low output voltage ripple. output voltage programming the ISL9110A is available in fixed and adjustable output voltage versions. to use the fixed output version, the vout pin must be connected directly to fb. in the adjustable output voltag e version (ISL9110Aiitaz), an external resistor divider is required to program the output voltage. the fb pin has very low input leakage current, so it is possible to use large value resistors (e.g. r1 = 1m ? and r2 = 324k ? ) in the resistor divider connected to the fb input. applications information component selection the fixed-output version of the ISL9110A requires only three external power components to implement the buck boost converter: an inductor, an input capacitor, and an output capacitor. the adjustable ISL9110A versions require three additional components to program the output voltage. two external resistors program the output voltage, and a small capacitor is added to improve stability and response. an optional input supply filtering capacitor (?c3? in figure 28) can be used to reduce the supply noise on the vin pin, which provides power to the internal reference. in most applications, this capacitor is not needed. figure 27. buck boost topology pvin vout switch a switch d switch b switch c lx1 lx2 l1 v out = 3.0v/1a vout a5 fb d5 c2 10f r1 r2 1m 365k bat pg status outputs d2 d1 pvin v in = 1.8v to 5.5v vin b1 c1 mode en d3 c2 c1 10f ISL9110Aiitaz d4 c3 lx1 lx2 b 2 a 4 l1 2.2h c4 56pf b5 gnd c5 b3 a3 c4 pgnd b 4 a 2 a1 c3 1f figure 28. typical ISL9110Aiitaz application
ISL9110A 13 fn8299.1 june 8, 2012 output voltage programming, adj. version setting and controlling the output voltage of the ISL9110Aiitaz (adjustable output version) can be accomplished by selecting the external resistor values. equation 1 can be used to derive the r1 and r2 resistor values: when designing a pcb, include a gnd guard band around the feedback resistor network to reduce noise and improve accuracy and stability. resistors r1 and r2 should be positioned close to the fb pin. feed-forward capacitor selection a small capacitor (c4 in figure 28) in parallel with resistor r1 is required to provide the specified load and line regulation. the suggested value of this capacitor is 56pf for r1 = 1m . an npo type capacitor is recommended. non-adjustable versio n fb pin connection the fixed output versions of the ISL9110A does not require external resistors or a capacitor on the fb pin. simply connect v out to fb, as shown in figure 29. inductor selection an inductor with high frequency core material (e.g. ferrite core) should be used to minimize core losses and provide good efficiency. the inductor must be able to handle the peak switching currents without saturating. a 2.2h inductor with 2.4a saturation current rating is recommended. select an inductor with low dcr to provide good efficiency. in applications where radiated noise must be minimized, a toroidal or shielded inductor can be used. pvin and v out capacitor selection the input and output capacitors sh ould be ceramic x5r type with low esl and esr. the recommended input capacitor value is 10f. the recommended v out capacitor value is 10f to 22f. application example 1 an application using the fixed-output ISL9110Aiitnz is shown in figure 30. this application requires only three external components. application example 2 an application requiring v out = 3.0v, using the adjustable-output ISL9110Aiitaz is shown in figure 31. this application requires six external components. recommended pcb layout correct pcb layout is critical for proper operation of the ISL9110A. the input and output capacitors should be positioned as closely to the ic as possible. the ground connections of the input and output capacitors should be kept as short as possible, and should be on the component layer to avoid problems that are caused by high switching currents flowing through pcb vias. table 1. inductor vendor information manufacturer series website coilcraft lps4018 www.coilcraft.com murata lqh44p www.murata.com taiyo yuden nrs4018 nrs5012 www.t-yuden.com sumida cdrh3d23/hp cdrh4d22/hp www.sumida.com toko dem3518c www.toko.co.jp v out 0.8v 1 r1 r2 ------- - + ?? ?? ? = (eq. 1) figure 29. typical ISL9110Aiitnz application v out = 3.3v/1a vout a5 fb d5 c2 10f bat pg status outputs d2 d1 pvin v in = 1.8v-5.5v vin b1 c1 mode en d3 c2 c1 10f ISL9110Aiitnz d4 c3 lx1 lx2 b 2 a 4 l1 2.2h b5 gnd c5 b3 a3 c4 pgnd b 4 a 2 a1 table 2. capacitor vendor information manufacturer series website avx x5r www.avx.com murata x5r www.murata.com taiyo yuden x5r www.t-yuden.com tdk x5r www.tdk.com figure 30. typical ISL9110Aiitnz application v out = 3.3v/1a vout a5 fb d5 c2 10f bat pg status outputs d2 d1 pvin v in = 1.8v-5.5v vin b1 c1 mode en d3 c2 c1 10f ISL9110Aiitnz d4 c3 lx1 lx2 b 2 a 4 l1 2.2h b5 gnd c5 b3 a3 c4 pgnd b 4 a 2 a1 figure 31. typical ISL9110Aiitaz application v out = 3.0v/1a vout a5 fb d5 c2 10f r1 r2 1m 365k bat pg status outputs d2 d1 pvin v in = 1.8v-5.5v vin b1 c1 mode en d3 c2 c1 10f ISL9110Aiitaz d4 c3 lx1 lx2 b 2 a 4 l1 2.2h c4 56pf b5 gnd c5 b3 a3 c4 pgnd b 4 a 2 a1
ISL9110A 14 fn8299.1 june 8, 2012 figure 32. recommended ISL9110Aiitnz pcb layout figure 33. recommended ISL9110Aiitaz pcb layout
ISL9110A 15 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn8299.1 june 8, 2012 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog sign al processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: ISL9110A to report errors or suggestions for this datasheet, please go to www.intersil.com/askourstaff fits are available from our website at http://rel.intersil.com/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change may 29, 2012 fn8299.1 corrected ?pin configuration? on page 2. may 11, 2012 fn8299.0 initial release.
ISL9110A 16 fn8299.1 june 8, 2012 package outline drawing w4x5.20a 20 ball wafer level chip scale package (wlcsp) rev 1, 1/12 0.2700.03 0.1750.03 0.530 max 0.3000.025 seating plane z bottom view side view typical recommended land pattern top view pin 1 (a1 corner) package outline 0.400 0.225 0.10 (4x) 0.275 x y 1.5950.02 2.3350.02 1.200 0.400 0.400 1.600 0.367 20x 0.2700.03 ab c d 0.200 1 2 3 4 5 0.197 0.10 z x y 0.05 z 3 0.05 z 1. dimensions and tolerance per asme y 14.5m - 1994. 2. dimension is measured at the maximum bump diameter parallel to primary datum z. 3. primary datum z and seating plane are defined by the spherical crowns of the bump. 4. bump position designation per jesd 95-1, spp-010. 5. there shall be a minimum clearance of 0.10mm between the edge of the bump and the body edge. notes:

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